| Name | Version | Summary | date |
| peakrdl-busdecoder |
0.2.0 |
Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces |
2025-10-27 02:44:57 |
| peakrdl-python |
2.0.0 |
Generate Python Register Access Layer (RAL) from SystemRDL |
2025-10-25 10:35:12 |
| peakrdl-rust |
0.2.1 |
Generate a Rust crate from SystemRDL for accessing control/status registers. |
2025-10-11 14:42:31 |
| peakrdl-regblock-vhdl |
1.1.0.0 |
Compile SystemRDL into a VHDL control/status register (CSR) block |
2025-09-17 13:39:57 |
| peakrdl-viz |
1.0.2 |
Generate visualization code for MakerChip VIZ framework. |
2025-08-13 18:29:39 |
| peakrdl-regblock |
0.23.0 |
Compile SystemRDL into a SystemVerilog control/status register (CSR) block |
2024-12-20 06:06:20 |
| peakrdl |
1.2.3 |
Toolchain for control/status register automation and code generation. |
2024-12-17 06:42:29 |
| peakrdl-cli |
1.2.3 |
Command-line tool for control/status register automation and code generation. |
2024-12-17 06:41:36 |
| peakrdl-ipxact |
3.5.0 |
Import and export IP-XACT XML to/from the systemrdl-compiler register model |
2024-10-15 04:45:01 |
| peakrdl-docx |
0.4.7 |
Compile SystemRDL definition into a Docx (MsWord) document |
2024-09-19 08:54:40 |
| peakrdl-beam |
0.1.0 |
Generate Erlang or Elixir modules from a SystemRDL register model |
2024-08-02 14:53:16 |